In recent years, various high-speed serial communication technologies have been developing with an increase in communication speed of data communication. In high-speed serial communication in which baseband transmission is the mainstream, a waveform of a data transmission signal deteriorates in proportion to a frequency of the data transmission signal due to skin effect and dielectric loss in a transmission path. For this reason, there is a disadvantage in that deterioration of the waveform exerts on neighboring bits and subsequent bits; and consequently, data communication is not correctly performed. Such interference to other communication codes is called as intersymbol interference, and there is reported a waveform equalizing technique which solves such intersymbol interference. That is, as one of transmission systems for correcting the intersymbol interference in baseband transmission, there is a partial response (hereinafter referred to as PR) system that is a system for equalizing a code so as to discretely take an amount of the intersymbol interference. In duobinary transmission that is one of the PR system, successive two pulses discretely having one symbol time interval are combined and transmitted.
As shown in FIG. 1, combined signal waves have regions A, B, C, D, and the like in data eye openings; signal formats with three data levels at the receiving end; and complicated data transition different from pulse amplitude modulation (referred to as PAM) transmission such as binary and quaternary transmission. A clock of the received data needs to be correctly reproduced from such complicated transition data.
Conventionally, as for this kind of technology, there is one disclosed in the following document, for example. In a digital signal reproducing apparatus disclosed in Patent Document 1, a sampling clock of an A/D converter circuit is sampled (oversampled) by a clock having a cycle four times as long as the data cycle. In the case where electric potentials of neighboring sampling data having the same codes are different, in order to show that the sampling clock is not sampled at the center of a data waveform, analog values sampled by the A/D converter circuit are matched, and accordingly, a phase of a reproducing clock is adjusted at an optimum position. However, in high-speed serial communication, amplitude attenuation in a data transmission path is very large, and therefore, it is very difficult to detect an analog potential of received data with high accuracy by the A/D converter circuit. Furthermore, in the same reproducing apparatus, in order to take a time for adjusting the clock, data transmission in which a phase adjustment signal header is applied to data is performed. During this time, since data to be fundamentally communicated cannot be communicated, there is a problem in that effective communication speed is reduced. In order not to reduce communication speed, the clock is required to be reproduced from communicating data itself.    [Patent Document 1] Japanese Patent Laying-Open No. 06-176498 (Abstract, FIG. 1, FIG. 2, and FIG. 4)